Transistors, such as field effect transistors (FETs), have become ubiquitous in modern electronics and are employed to perform amplifier or switching functions in applications ranging from power amplifiers to digital processors. In many applications, either the need for additional functionality or miniaturization has led to aggressive downsizing of transistors. Unfortunately, the physical laws and material limits prevent continuous downsizing and require new approaches for increasing speed and functionality.
In general, FETs rely on an electric field applied at a gate terminal to control the conductivity of a semiconductor channel extending between the source and drain terminals of the transistor. The electrical conductivity of the semiconductor channel corresponds to the rate at which electrons or holes flow between the source and drain terminals, and has a direct impact on the performance and switching speeds of the FET. The flow of electrons or holes in the semiconductor channel is governed by the carrier mobility, a parameter, which defines how fast electrons or holes react to an applied electric field. Unfortunately, aggressive downsizing of FETs makes it hard to maintain the carrier mobility within the semiconductor channel, since the physical size of the semiconductor channel impacts carrier mobility. All things being equal, as the size of the semiconductor channel decreases, the room-temperature carrier mobility within the semiconductor channel decreases.
Strain engineering has been employed to improve carrier mobility in the relatively small semiconductor channels. The crystal lattice of the material forming a semiconductor channel is formed from an atomic structure. With strain engineering, thin films are applied to either side of a channel layer that provides the semiconductor channel. The thin films and the channel layer will have different lattice structures, and in particular, the bonds between atoms in the thin films will normally have different spacing than the bonds between the atoms in the channel layer. The thin films and the channel layer are formed such that the thin films on either side of the channel layer either stretch or compress the bonds between the atoms in the crystal lattice of the channel layer. Interestingly, certain types of FETs benefit from placing the channel layer under tension, while others benefit from compression. For example, electron mobility in P-type FETs increases when the channel layer is under tension, while hole mobility increases in N-type FETs when the channel layer is under compression.
In complementary metal-oxide semiconductor (CMOS) processes, N-type and P-type transistors are paired in a complementary and symmetrical fashion to provide various logic functions. To benefit from the enhanced carrier mobility provided by strain engineering, the individual N- and P-type FETs on a given wafer must be subjected to either tension or compression. Having to provide different types of strain to large numbers of FETs on a given wafer significantly increases process complexity, reliability, and expense.
Although strain engineering improves carrier mobility, thermal performance suffers. Layers of silicon germanium (SiGe) or other alloys of silicon (Si) are often used as the thin films for a silicon-based semiconductor channel. Silicon germanium and the other alloys are generally poor thermal conductors relative to the semiconductor channel and surrounding layers. For example, silicon germanium has a thermal conductivity an order of magnitude less than that of silicon. As such, application of strain engineering significantly reduces the efficiency at which heat is transferred out of the semiconductor channel, thereby limiting operating speeds and current handling.
Accordingly, there is a need for an efficient and effective technique to improve carrier mobility in transistor architectures without requiring strain engineering techniques. There is a further need for a technique to improve carrier mobility without significantly degrading thermal performance of the transistor architectures. There is also a need for improved carrier mobility while maintaining thermal performance in small-scale transistor architectures.